Chip Creator GUI is a user-friendly tool for IC designers. It excels in large designs with its linear design capability, supports multiple CPUs with a single license, and fosters teamwork through network files. It easily creates, verifies, and edits chip layouts. At the completion of the chip design, you can easily read/view the log file or report generated in the notepad. It is suggested to use a third-party tool to verify the chip layout to ensure the design is flawless.
Before proceeding with the Chip Creator GUI Tool, ensure you meet the following prerequisites:
Set the environment variable TOOL_HOME to the directory of the installed Chip Creator tool through the command:
setenv TOOL_HOME <path_to_Chip_Creator>
Replace <path_to_Chip_Creator> with the appropriate directory path on your system.
Run the chip_creator_app executable to launch the Chip Creator tool through command:
$TOOL_HOME/bin/chip_creator_app
Use the command start_gui in <CC_PROMPT> in the command line to launch the Graphical User Interface of the tool.
Go to the 'File' menu and select 'Open Design' to import the library and design.
Library files to be imported include cells.lef, tech.lef, timing.lib, and design.netlist.
Optionally, you can load old project files.
Alternatively, enter the read_file command in the GUI prompt for importing the library and design. (Note: The tech.lef must be read first.)
To verify that all readings are correct, use 'Verify > Inputs' in the menu bar. Once verified, the tool is ready for the next steps.
If there are 'INFO' messages in the verification report, these indicate the files that were read before this step.
Before creating the chip outline, consider the following key points:
Create the chip outline using one of the following options:
create_outline command with the desired value.-all option.Note - Cell is displayed on the GUI after placing done.
connect command.set_layers command. Note - If wires don't connect, consider running the place_cells command again. 'Place All Cells' option has a random algorithm which can cause issues in wire connections.
With the above procedure, you will have successfully used the Chip Creator tool to style and create a chip layout that can be sent for manufacturing in integrated circuit packages.